This invention relates to a method for and apparatus for tape automated bonding (TAB) for integrated circuits (ICs). More particularly, this invention relates to a method for producing three layer conductive foil, adhesive and polymer film TAB substrates with a support ring in the feature window; and this invention also relates to the structure of a three layer TAB substrate with a support ring in the feature window.
The general process of tape automated bonding for integrated circuits is known in the art. The TAB process requires the production and use of a substrate having a feature window into which the integrated circuit is placed for connection to circuitry.
In current standard practice there are two commonly used methods for making three layer TAB substrates. One method consists of the following steps:
(1) slit the insulating material to desired width; PA0 (2) laminate adhesive to one side of the insulating film the adhesive width being less than the width of the insulating material; PA0 (3) punch sprocket holes along the side boundaries of the film strip and punch feature windows aligned along the center axis of the film strip; PA0 (4) laminate copper foil to the adhesive coated side of the film strip and cure to bond. PA0 (1) coat on insulating material (prior to slitting to width) full width with an adhesive originally in the form of a wet film; PA0 (2) slit the material of (1) to desired width; PA0 (3) punch sprocket holes along the side boundaries of the film strip and punch feature windows aligned along the center axis of the film strip; PA0 (4) laminate copper foil to the adhesive coated side of the film strip and cure to bond.
The second method consists of the following steps:
Subsequent to these steps for preparing the TAB substrate, desired circuit patterns with interconnect leads will be printed in the copper foil, and an integrated circuit will be positioned in the feature window and connected to lead lines of the circuitry.
A significant problem exists in the prior art in that the lead lines between the circuitry and the IC are unsupported in the area of the feature window. This makes it very difficult to achieve and maintain desired alignment between lead lines and bond sites on the IC, especialy in view of the dimensions involved in IC technology and both the narrow width of both the lead lines and the narrow spacing between the lead lines.